IBM Scientists Demonstrate Liquid Cooling Process for 3D Stacked Chips

IBM scientists say stacked processors have higher power densities than nuclear reactors

As processors add processing cores, circuits, and other components, the amount of heat they generate increases exponentially. Researchers and chipmakers have found that the ability to dissipate heat will be one of the main challenges to making processors in the future.

Researchers from IBM Labs and the Fraunhofer Institute in Berlin have demonstrated a prototype 3D chip that has a liquid cooling system built-in to deliver water directly between each layer of the stacked processor.

The 3D chip stacks take components in a traditional chip that sit side-by-side and stack them atop one another in a layer. While the process allows chipmakers to create more powerful chips, with shortened interconnects between components for data to travel, the process presents significant cooling challenges. With 3D stacked chip design data has to move only 1/1000th of the distance data needs to travel on a traditional 2D chip. In addition to the shortened pathways for data to traverse, the 3D process also allows for 100 times the amount of pathways for data to flow. Both techniques together greatly increase the potential performance of a 3D stacked chip.

The issue for researchers designing these 3D chips is that the stacked chips produce a very high level of aggregated heat dissipation of close to 1 kilowatt in a volume of only half a cubic centimeter. IBM researchers point out that that level of heat dissipation is 10 times higher than any other human-made device and that power densities in stacked processor designs are higher than in both nuclear and plasma reactors.

Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory said in a statement, “As we package chips on top of each other to significantly speed a processor's capability to process data, we have found that conventional coolers attached to the back of a chip don't scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling. Until now, nobody has demonstrated viable solutions to this problem.”

The solution to the problem the IBM team devised is to pipe water through cooling structures, as thin as 50 microns, between the individual layers of the stacked chip. The scientists were able to show cooling performance of up to 180 W/cm2 per layer in a stack with a footprint of 4 cm2. One IBM researcher says that the cooling performance is a significant breakthrough and that without the breakthrough the stacking of two or more high-density power layers would be impossible.

In experiments, the researchers passed water into a 1 by 1 cm test device made up of a cooling layer between two heat sources. The cooling layer was only 100 microns in height (about twice the thickness of a human hair) and has 10,000 vertical interconnects per square cm.

The interconnects were hermetically sealed to prevent the water from causing electrical shorts within the chip. Individual layers were built using existing 3D packaging fabrication methods to etch the holes for signal transmission from one layer to the next. Each interconnect had a silicon wall around it and a fine layer of silicon oxide to insulate the electrical connections from the water. A new thin-film soldering technique was developed by the researchers to provide the precision and robustness needed to provide thermal contact for the cooling film.

IBM first announced its 3D chip stacking process in April of 2007.